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october 2011 doc id 16525 rev 3 1/33 33 stpms2 smart sensor ii dual-channel 1-bit, 4 mhz, second-order sigma-delta modu lator with embedded pglna features v cc supply range 3.2 v - 5.5 v two second-order sigma-delta ( ?) modulators programmable chopper- stabilized low noise and low offset amplifier supports 50-60 hz, en 50470-1, en 50470-3, iec 62053-21, iec 62053-22 and iec 62053- 23 standards specs for class 1, class 0.5 and class 0.2 ac watt meters stpm02h: less than 0.5% error over 1:10000 range stpm02l: less than 0.5% error over 1:5000 range precision voltage reference: 1.23 v with programmable tc (stpms2l only) internal low drop regulator @ 3 v (typ.) applications power metering motor control industrial process control weight scales pressure transducers description the stpms2, also called ?smart sensor? devices, are assps designed for ef fective measurement in power line systems utilizing rogowski coil, current transformer, hall or shunt sensors. these devices are designed as building blocks for single-phase or multi-phase energy meters along with the stpmc1 device, a digital signal processor designed for energy measurement. this device can be used in medium and high resolution measurement applications where single or double inputs must be monitored at the same time. the stpms2 are mixed signal ics consisting of an analog and digital section. the analog section consists of a programmable gain, low noise choppered amplifier, two second-order ? modulator blocks, a band-gap voltage reference, a low-drop voltage regulator and dc buffers, while the digital section consists of a clock generator and output multiplexer. qfn16 (4 x 4) table 1. device summary order codes package packaging STPMS2H-PUR qfn16 (4 x 4 mm) 4500 parts per reel stpms2l-pur qfn16 (4 x 4 mm) 4500 parts per reel www.st.com
contents stpms2 2/33 doc id 16525 rev 3 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1 general operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.2 functional description of the analog part . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.3 functional description of the digital part . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.3.1 decoder for different modes of operation . . . . . . . . . . . . . . . . . . . . . . . 21 8.3.2 generator for clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.4 hard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 soft mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.5.1 writing to the configuration register in soft mode . . . . . . . . . . . . . . . . . 27 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
stpms2 introduction doc id 16525 rev 3 3/33 1 introduction the stpms2 is a device designed to meas ure electrical line parameters (voltage and current) via analog signals from voltage sensors (current divider) and current sensors (inductive rogowski coil, current transformer or shunt resistors). the device is used together with a digital signal processing circuit to implement an effective measuring system for multi-phase power meters. the device consists of two analog measuring channels, consisting of second-order sigma- delta modulators with appropriate non-overlapping control signal generator. the stpms2 also includes a temperature compensated band-gap reference voltage generator, a low- drop supply voltage stabilizer and minimal digital circuitry that includes bist (built-in self- test) structures. in a current signal processi ng channel, a low-noise preamplifier is included in front of the sigma-delta converter. all reference voltages (band-gap, agnd) are internally buffered to eliminate channel crosstalk. the stpms2 can operate in fast or low-power mode. in fast mode, a nominal clock frequency of 4.1 or 4.9 mhz is applied to the clock input. in this mode, signal bandwidth is specified between 0 and 4 khz. in low-power mode, the nominal clock is four times slower in order to reduce the power consumption of the circuit. in low-power mode, the quiescent bias currents of the preamplifier and sigma-delta integrators are lowered and the signal bandwidth is narrowed to the frequency bandwidth of 0 to 1 khz.
internal block diagram stpms2 4/33 doc id 16525 rev 3 2 internal block diagram figure 1. stpms2 internal block diagram cip cin vip vin vcc vdda vddac gnd vddav vbg ms1 clk dat ms3 ms0 datn ms2 mux 2nd ord ? modulator bist dac 2nd ord ? modulator mux plna ldr voltage reference vrefv vrefc digital front end gain tc einchpc, einchpv gain einchpc einchpv echplfc, echphfc mc, nc pdv echplfv, echphfv mv, nv eprsv eprsv am09 8 92v1
stpms2 pin configuration doc id 16525 rev 3 5/33 3 pin configuration figure 2. pin connections am09 38 2v1 1 vddac vdda vbg m s 1 m s 0 vcc m s 2 vddav datn clk m s3 dat vip cip cin vin gnd 2 3 4 56 7 8 9 10 11 12 16 15 14 1 3 table 2. pin description pin n symbol description 1 vcc unregulated supply voltage for pad-ring, bandgap, low-drop and level shifters 2 vddac current channel modulator supply input 3 vdda output of internal + 3.0 v low drop regulated power supply 4 vbg output of internal + 1.23 v bias generator (stpms2l); input of external precision reference voltage (stpms2h) 5 cin current channel - 6 cip current channel + 7 vin voltage channel - 8 vip voltage channel + 9 vddav voltage channel modulator supply input 10 ms0 input for configurator 0 11 ms1 input for configurator 1 12 ms2 input for configurator 2 13 ms3 input for configurator 3 14 clk input for external measurement clock 15 dat output of multiplexed ? signal output of current ? signal 16 datn output of inverted multiplexed ? signal output of voltage ? signal exp pad gnd ground level for signals and pin protection
maximum ratings stpms2 6/33 doc id 16525 rev 3 4 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 3. absolute maximum ratings symbol parameter value unit v cc dc input voltage -0.3 to 6 v i pin current on any pin (sink/source) 150 ma v id input voltage at any pin -0.3 to v cc +0.3 v v ia input voltage at analog pins (vip, vin, iip, iin) -0.7 to 0.7 v esd human body model (all pins) 2 kv t op operating ambient temperature -40 to 85 c t j junction temperature -40 to 150 c t stg storage temperature range -55 to 150 c table 4. thermal data symbol parameter value unit r thja (1) thermal resistance junction-ambient 38.66 c/w 1. this value is referred to single-layer pcb, jedec standard test board.
stpms2 maximum ratings doc id 16525 rev 3 7/33 4.1 general operating conditions v cc = 5 v, t amb = 25 c, 1 f between v cc , vdda, vddac, vddav and gnd, 100 nf between vbg and gnd, f clk = 4.19 mhz unless otherwise specified. table 5. general operating conditions symbol parameter test conditions min. typ. max. unit general section v cc operating supply voltage 3.135 5.25 v i cc quiescent current lp, 1.229mhz; v cc =3.3v; c l =100nf; no loads 1.2 1.5 ma hp, 4.915mhz; v cc =3.2v; c l =100nf; no loads 45 v por power on reset on v cc 2.5 v v dd regulated supply voltage 1.049mhz; v cc =3.2v; c l =100nf; no loads 2.95 3.00 3.05 v i latch current injection latch- up immunity 300 ma f bw effective bandwidth limited by chopper 0 4091 hz dc measurement accuracy resolution 11 16 bit inl integral non linearity result referred to a 16-bit word of cip- cin channel, hp mode, f clk = 2.047mhz 3.3 lsb result referred to a 12-bit word of vip- vin channel, hp mode, f clk =2.047mhz 3.9 dnl differential linearity result referred to a 16-bit word of cip- cin channel, hp mode, f clk =2.047mhz 0.3 lsb result referred to a 12-bit word of vip- vin channel, hp mode, f clk =2.047mhz 0.5 offset error result referred to a 16-bit word of cip- cin channel, hp mode, f clk =2.047mhz 0.02 lsb result referred to a 12 bit-word of vip- vin channel, hp mode, f clk =2.047mhz 0.005 gain error result referred to a 16-bit word of cip- cin channel, hp mode, f clk =2.047mhz 0.04 0.4 lsb/uv result referred to a 12-bit word of vip- vin channel, hp mode, f clk =2.047mhz 0.003 nf noise floor cip-cin channel gain 2x 120 db cip-cin channel gain 16x 118 vip-vin channel 95
maximum ratings stpms2 8/33 doc id 16525 rev 3 symbol parameter test conditions min. typ. max. unit psrr dc power supply dc rejection voltage signal: 200 mv rms /50hz current signal: 10 mv rms /50hz f clk =2 . 048 mhz v cc =3.3v 10%, 5v 10% 90 db ac measurement accuracy snr signal to noise ratio cip-cin channel ? vin=230mv @ 55hz gain 2x over 4 khz bandwidth 82 db vip-vin channel ? vin=230mv @ 55hz over 4 khz bandwidth 52 sinad signal to noise ratio + distortion cip-cin channel ? vin=230mv @ 55hz gain 2x over 4 khz bandwidth 82 db vip-vin channel ? vin=230mv @ 55hz over 4 khz bandwidth 52 thd total harmonic distortion cip-cin channel ? vin=230mv @ 55hz gain 2x over 4 khz bandwidth -105 db vip-vin channel ? vin=230mv @ 55hz over 4 khz bandwidth -78 sfdr spurious free dynamic range cip-cin channel ? vin=230mv @ 55hz gain 2x over 4 khz bandwidth 90 db vip-vin channel ? vin=230mv @ 55hz over 4 khz bandwidth 68 psrr ac power supply ac rejection voltage signal: 200 mv rms /50hz current signal: 10 mv rms /50hz f clk =2 . 048 mhz v cc =3.3v+0.2v rms 1@100hz v cc =5.0v+0.2v rms 1@100hz 120 db analog inputs (cip, cin, vip, vin) v max maximum input signal levels vip-vin channel -0.3 +0.3 v stpms2l cip-cin channel gain 2x gain 4x gain 8x gain 16x stpms2h cip-cin channel -0.3 -0.15 -0.075 -0.0375 -v ref / gain +0.3 +0.15 +0.075 +0.0375 +v ref / gain v f spl a/d sampling frequency f clk hz v off amplifier offset 20 mv z ip vip, vin impedance over total operating voltage range 100 400 k z in cip, cin impedance over total operating voltage range 35 50 k g err gain error of current channels 10 % table 5. general operating conditions (continued)
stpms2 maximum ratings doc id 16525 rev 3 9/33 symbol parameter test conditions min. typ. max. unit i ilv voltage channel leakage current v cc =5.25v, f clk =4.19mhz -1 1 a i ili current channel leakage current v cc =5.25v, f clk =4.19mhz -1 1 v cc =5.25v, f clk =4.19mhz input enabled -10 10 crosstalk between channels 130 db digital i/o (clk, dat, datn, ms0, ms1, ms2, ms3) v ih input high voltage 0.75v c c 5.3 v v il input low voltage -0.3 0.25v c c v v oh output high voltage i o =-1ma, c l =50pf, v cc =3.2v v cc -0.4 v v ol output low voltage i o =+1ma, c l =50pf, v cc =3.2v 0.4 v i up pull up current 15 a t tr transition time c load =50pf 10 ns t l latency from 50% of clk to 50% to dat 40 ns clock input f clk nominal frequencies low precision mode 1.0 1.228 mhz high precision mode 2.0 2.458 very high precision mode 4.0 4.915 on chip reference voltage v ref reference voltage stpms2l only (1) 1.21 1.23 1.25 v z out output impedance 30 200 k i l maximum load current 0 a t c temperature coefficient after calibration 30 50 ppm/c 1. this level may be delivered from external source in stpms2h. table 5. general operating conditions (continued)
maximum ratings stpms2 10/33 doc id 16525 rev 3 clk - clock signal on clk pin clk sample - sigma-delta sampling frequency bsv - sigma-delta bit stream of voltage signal bsc - sigma-delta bit stream of current signal data - multiplexed data of voltage and current signal on dat pin figure 3. timing diagram am09383v1
stpms2 application doc id 16525 rev 3 11/33 5 application the choice of external components in the transduction section of the application is a crucial point in the application design, affecting the precision and the resolution of the entire system. among the several considerations, a compromise should be found between the following requirements: 1. maximize the signal-to-noise ratio in the voltage and current channel 2. choose the current-to-voltage conversion ratio ks and the voltage divider ratio in a way that calibration can be achieved 3. choose ks to take advantage of the whole current dynamic range in accordance with desired maximum current and resolution. to maximize the signal-to-noise ratio of the current channel, the voltage divider resistors ratio should be as close as possible to those shown in ta bl e 6 . figure 4 below provides a reference application schematic diagram: p = 64000 imp/kwh i nom = 5 a i max = 60 a typical sensitivity values for the current sensors are indicated in ta b l e 6 . figure 4. detailed application schematic u1 s tpm s 2h/l vd d 1 vd d a c 2 vd d a 3 vbg 4 cin 5 cip 6 vin 7 vip 8 vd d a v 9 m s 0 10 m s 1 11 m s 2 12 m s3 1 3 clk 14 dat 15 datn 16 e1 17 e2 1 8 e 3 19 e4 20 c5 1 c6 1 c14 1 c9 1 l load n vc c clk r7 1k 1 % r6 3 . 3 1 % r 8 1k 1 % c7 4.7n c 8 4.7n l 3 e4622_x50 3 r4 150k r 3 150k r2 150k c 3 10n r5 470 1 % clk dat m s 0 = clk hp ampl x4 m s 1 = 0 tc = 50 ppm/ r c m s 2 = 0 volt a ge ch a nnel on, dat =(clk)? bs v: bs c m s3 = 0 h a rdmode, bi s t mode off l1 1 vl vn am09 3 79v1
application stpms2 12/33 doc id 16525 rev 3 note: above listed components refer to typical metering application. anyhow, stpms2 operation is not limited to the choice of these external components. table 6. recommended external components in metering applications function component description value tolerance unit calculator stpmc1 --- --- --- --- line voltage interface resistor divider r to r ratio v rms =230v 1:1650 1% 50ppm/c v/v r to r ratio v rms =110v 1:830 line current interface rogowski coil current-to-voltage ratio k s 0.15 5% 50ppm/c mv/a ct 1.7 5% shunt 0.43 5% figure 5. simplified application schematics for stpmc1 based energy metering am09 8 9 3 v1 r s t n load current sensor ant i al i a s i ng ne t wo r k cin cip gnd vcc vdd dat dat n cl k m s 1 m s 0 m s 3 m s 2 vbg vip vin cur r ent sensor ant i al i a s i ng ne t wo r k cin cip gnd vcc vdd dat dat n cl k m s 1 m s 0 m s 3 m s 2 vbg vip vin cur r ent sensor ant i al i a s i ng ne t wo r k cin cip gnd vcc vdd dat dat n cl k m s 1 m s 0 m s 3 m s 2 vbg vip vin calc ulat or stpm c1a dat cl k das dar
stpms2 application doc id 16525 rev 3 13/33 figure 6. connection schematics for dsp-based applications am09 38 0v1 clkout datin d s p cin cip gnd vcc vdd dat datn clk m s 1 m s 0m s3 m s 2 vbg vip vin s en s or 1 anti ali as ing network s en s or 2 anti ali as ing network
terminology stpms2 14/33 doc id 16525 rev 3 6 terminology 6.1 conventions the lowest analog and digital power supply voltage is called gnd which represents the system ground. all voltage specifications for digital input/output pins are referred to gnd. the highest power supply voltage is called v cc . the highest core power supply is internally generated and is called v dd . positive currents flow into a pin. sinking current means that the current is flowing into the pin and thus it is positive. sourcing current means that the current is flowing out of the pin and thus it is negative. a positive logic convention is used in all equations. 6.2 notation output bit streams of the modulator are indicated as bsv and bsc for voltage and current channels, respectively.
stpms2 typical performance characteristics doc id 16525 rev 3 15/33 7 typical performance characteristics figure 7. v ref /v ref at 25 deg vs. temp figure 8. snhr of i channel, gain 16x figure 9. snhr of i channel, gain 2x figure 10. snhr of v channel, gain 2x figure 11. sinad of i chan nel, gain 16x (temp. variation) figure 12. sinad of i channel, gain 16x (temp. variation) am09901v1 -10 0 10 20 30 40 50 60 70 80 90 10 100 1000 10000 100000 1000000 snhr [db] i peak-peak [v] current 16x, fsig = 55hz, hp mode 2.047mhz, 3.3v, -30deg current 16x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 0deg current 16x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 25deg current 16x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 60deg current 16x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 85deg am09902v1 -20 -10 0 10 20 30 40 50 60 70 80 90 10 100 1000 10000 100000 1000000 10000000 snhr [db] i peak-peak [v] current 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, -30deg current 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 0deg current 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 25deg current 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 60deg current 2x, fsig = 55hz, lp mode 2.047mhz, 3.3v, 85deg am0990 3 v1 -40 -30 -20 -10 0 10 20 30 40 50 60 100 1000 10000 100000 1000000 10000000 snhr [db] u peak-peak [v] voltage 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, -30deg voltage 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 0deg voltage 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 25deg voltage 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 60deg voltage 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 85deg am09904v1 -10 0 10 20 30 40 50 60 70 80 90 10 100 1000 10000 100000 1000000 sinad [db] i peak-peak [v] current 16x, fsig = 55hz, hp mode 2.047mhz, 3.3v, -30deg current 16x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 0deg current 16x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 25deg current 16x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 60deg current 16x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 85deg am09905v1 -40 -30 -20 -10 0 10 20 30 40 50 60 100 1000 10000 100000 1000000 10000000 sinad [db] u peak-peak [v] voltage 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, -30deg voltage 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 0deg voltage 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 25deg voltage 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 60deg voltage 2x, fsig = 55hz, hp mode 2.047mhz, 3.3v, 85deg
typical performance characteristics stpms2 16/33 doc id 16525 rev 3 figure 13. relative gain error of i channel, gain 16x figure 14. relative gain error of i channel, gain 2x am09 8 99v1 0.9 0.92 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 1.1 10 100 1000 10000 100000 1000000 i peak-peak [v] relative gain error [ - ] current 32x, fsig = 55hz, hp mode 2.455mhz, 3.3v current 32x, fsig = 55hz, hp mode 2.455mhz, 5.0v current 32x, fsig = 55hz, hp mode 2.047mhz, 3.3v current 32x, fsig = 55hz, hp mode 2.047mhz, 5.0v current 32x, fsig = 55hz, lp mode 1.229mhz, 3.3v current 32x, fsig = 55hz, lp mode 1.229mhz, 5.0v current 32x, fsig = 55hz, lp mode 1.048mhz, 3.3v current 32x, fsig = 55hz, lp mode 1.048mhz, 5.0v am09900v1 0.9 0.92 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 1.1 10 100 1000 10000 100000 1000000 10000000 i peak-peak [v] relative gain error [ - ] current 4x, fsig = 55hz, hp mode 2.455mhz, 3.3v current 4x, fsig = 55hz, hp mode 2.455mhz, 5.0v current 4x, fsig = 55hz, hp mode 2.047mhz, 3.3v current 4x, fsig = 55hz, hp mode 2.047mhz, 5.0v current 4x, fsig = 55hz, lp mode 1.229mhz, 3.3v current 4x, fsig = 55hz, lp mode 1.229mhz, 5.0v current 4x, fsig = 55hz, lp mode 1.048mhz, 3.3v current 4x, fsig = 55hz, lp mode 1.048mhz, 5.0v figure 15. accuracy over dynamic range am09906v1 0.097% 0.076% 0.040% 0.035% -0.008% 0.027% 0.035% -0.065% -0.087% -0.096% -0.087% -0.096% -0.096% -0.352% -0.435% -0.487% -0.6% -0.5% -0.4% -0.3% -0.2% -0.1% 0.0% 0.1% 0.2% 0.3% 0.4% 0.5% 0.01% 0.10% 1.00% 10.00% 100.00% 1000.00% aw e rro r [%] % of fs class 0.2 limits
stpms2 theory of operation doc id 16525 rev 3 17/33 8 theory of operation 8.1 general operation description the stpms2 performs second-order analog modulation of two channels in parallel, with appropriate non-overlapping control signal generator, of signals with frequencies varying from dc to 4 khz on two independent channels in parallel. the outputs of the converters provide two streams of digital ones and zeros which can be then be multiplexed in time to reduce the number of external connections. the stpms2 converts analog signals on two independent channels in parallel via delta- sigma ( ? ) analog-to-digital converters into a binary stream of sigma-delta signals. the device is particularly suitable to measure elec trical line parameters (voltage and current) via analog signals from voltage sensors (curr ent divider) and current sensors (inductive rogowski coil, current transformer or shunt resistors). there is a current channel for measuring line current and a voltage channel for measuring line voltage. the current channel input is connected through an external anti-aliasing rc filter to a rogowski coil, current transformer (ct) or shunt current sensor which converts line current into an appropriate voltage signal. the current channel includes a low-noise voltage preamplifier with programmable gain. the voltage channel is connected directly through a resistor voltage divider and anti-aliasing filter to a line voltage modulator (adc). both channels have quiescent zero signal point at gnd, so the stpms2 is able to sample differential signals on both channels with their zero point around gnd. the converted ? signals are multiplexed in time in order to reduce the number of external connections. the conversion and the multiplex are driven by external clock signal clk. the device is used in conjunction with a digita l signal processing circuit to implement an effective measuring system of a multi-phase power meter. the stpms2 also includes a temperature compensated band-gap reference voltage generator, low-drop supply voltage regulator and minimal digital circuitry that includes bist (built-in self-test) structures. in a current signal processing channel, a low-noise preamplifier is included upstream of the sigma-delta conver ter. all reference voltages are designed to eliminate channel crosstalk. the stpms2 can operate in fast (hp) or low-power (lp) mode (see also ta b l e 7 ). in fast mode, a nominal clock frequency of up to 4.1 / 4.9 mhz is applied to the clock input. in this mode, signal bandwidth is specified between 0 and 4 khz. in low-power mode, the nominal clock is four times slower (1 mhz) to lowe r the power consumption of the circuit. in low- power mode, the quiescent bias currents of the preamplifier and sigma-delta integrators are reduced and the signal bandwidth is narrowed to the frequency bandwidth of 0 to 1 khz. the mode of operation and configuration of the device can be selected by wiring configuration pins (ms0, ms1, ms2 and ms3) to v cc , gnd, clk or nclk signal. this approach can be used to change the settings of a current channel, sigma-delta stream output mode and temperature compensation curve of an internal band-gap reference. these pins can act as a serial port to change the configuration of the device. 8.2 functional description of the analog part the supply pins for the analog part are vcc, vdda, vddac, vddav, vbg and gnd. the gnd pin also represents a reference point. the vdda is an analog i/o pin of the internal +3.0 v low drop voltage regulator and the vddac and vddav are the modulator
theory of operation stpms2 18/33 doc id 16525 rev 3 supply inputs. a 1 f capacitor should be connected between vddxx and gnd. the input of the regulator is vcc, which also powers the band-gap and bias generators. the band-gap output is vbg, which should be connected to gnd via a 100 nf capacitor. the analog part of the stpms2 consists of: pre-amplifier in the current channel 1.23 v reference voltage generator (stpms2l only) +3 v low-drop supply voltage regulator two sigma-delta 2 nd order modulators bist dac agnd and v ref reference buffers bias current generators the voltage channel has a pre-amplification gain of 2, which defines the maximum differential voltage on voltage channel inputs to 300 mv. the relative gain of the current channel is selectable among 2, 4, 8 or 16, which defines the maximum differential voltage on the current channel to 300 mv, 150 mv, 75 mv or 37.5 mv, respectively. the full range of gains is available only in soft mode (see section 8.5 ), while in hard mode only 2 and 16 are selectable. the temperature-compensated reference voltage generator produces v ref = 1.23 v. this generator is implemented as a band gap generator, whose temperature compensation curve can be selected through configuration. the low drop regulator fixes and stabilizes the co re supply voltage to vdda = 3 v. all digital pads tolerate 5 v logic levels. the stpms2 is clocked by an external clock signal connected to pin clk. the stpms2l sigma-delta modulators work in several operating modes, shown in ta bl e 7 below. figure 16. power supply external connection scheme am09 38 1v1 vcc vddac vdda vbg ms1 ms0 ms2 vddav datn clk dat vip cip cin vin gnd ms3 an a log su pply 3 . 3 - 5.0 v 1 f 1 f 100 nf 1 f
stpms2 theory of operation doc id 16525 rev 3 19/33 lpr (low precision): f clk = 1 mhz and settings defined by ms0 through ms3 hpr (high precision): the normal mode of operation with f clk = 2 mhz to 4 mhz the stpms2h sigma-delta modulators work in the following mode: hhpr (very high precision) external reference must be connected to vbg, f clk = 4 mhz. the stpms2 performs operations in 2 basic modes: hard mode and soft mode. in hard mode the configuration is set through external pins ms0, ms1, ms2 and ms3. in soft mode, 40 configuration bits can be accessed through cfg[39:0], via serial communication. the pins used for serial communication are: ms0, ms1 and ms2. switching between hard and soft modes is achieved through pin ms3. hard mode : in this case the device configuration is bootstrapped at startup and signals come from vin and vip for voltage channels, and cip and cin for current channels or from internal bist dac. soft mode : in this mode all possible settings from hard mode are accessible, as well as the additional settings described in section 8.5 . the stpms2 sends to the dat and datn pins selected signals based on the configuration used. both outputs have cross-current and slew rate limiters to prevent excessive current spikes on supply lines. table 7. operating modes operating mode device f clk current consumption lp (low power) lpr (low precision) stpms2l 1 mhz 1,2 ma typ hp (fast) hpr (high precision) stpms2l 2 mhz ? 4mhz 4 ma typ hhpr (very high precision) stpms2h 4 mhz figure 17. block diagram of the modulator am09 8 94v1 - - d/a a 2 a 1 input stream out 1 st integrator 2 nd integrator comparator dithering
theory of operation stpms2 20/33 doc id 16525 rev 3 8.3 functional description of the digital part the digital section (dfe) includes: a decoder for different modes of operation a generator for clock frequency level shifters, pull-up stages and power buffers outside the dfe block figure 18. example of sigma-delta modulator output in case of sinusoidal waveform am09 8 95v1 figure 19. block diagram and definition of dfe digital signals am09 8 96v1 pseudo random chopper synchro mux decoder ms2 ms1 ms0 ms3 clk outputs for analog part sigma-delta streams clk clk dat datn clock generator clock signals domul dtmc
stpms2 theory of operation doc id 16525 rev 3 21/33 8.3.1 decoder for differ ent modes of operation the decoder defines the operating mode according to the state of the bootstrap ms0, ms1, ms2 and ms3 pins. two different operational modes can be defined: hard mode: in this case the device configuration is bootstrapped at startup and signals come from vin and vip for voltage channels, and cip and cin for current channels or from internal bist dac. soft mode: in this mode all po ssible settings from hard mode are accessible, as well as additional settings such as dither and c hopper signal frequencies and operation (see section 8.5 ). 8.3.2 generator for clock frequency chopper and bist frequency generator the chopper block generates the chopper frequencies and bist signals for the voltage and current channels. the bist dac output levels are appropriately adjusted for the current channel according to the gain selection, while for the voltage channel the max dc voltage is used. the levels are 300 mv for the voltage channel and 300 mv / 150 mv / 75 mv / 37.5 mv for the current channel, in accordance with gain settings 2/4/8/16, respectively, when operating in soft mode, while 300 mv / 37.5 mv based on gain settings 2/16 w hen operating in hard mode. pseudo random the pseudo random block generates pseudo random signals for the voltage and current channels. these random signals are used to implement a dithering technique to de- correlate the output of the modulators and avoid accumulation points on the frequency spectrum. synchro in synchro block the synchronization of sigma-delta input streams with strobe signals from analog part and clock signal is performed. mux in the mux block, which signals are connected to output pins dat and datn are selected. in hardmode, the output signals are selected by input pin ms2. in softmode, the output signals are selected by 8 configuration bits. 8.4 hard mode the stpms2 operates in hard mode when inpu t pin ms3 is connected to gnd or vcc, as described in ta b l e 1 1 . in hard mode, the stpms2 has four digital input pins (ms0, ms1, ms2 and ms3) to configure the basic operating parameters: bist dac enable temperature curve of reference voltage current and voltage channels settings output mode settings
theory of operation stpms2 22/33 doc id 16525 rev 3 in this way it is possible to access 128 different combinations, which are controlled through pins ms0, ms1, ms2 and ms3. ms0 sets the operating mode and amplifier gain selection as described in ta b l e 8 . for the stpms2l: ms0=gnd or clk to select lpr (low precision); f clk = 1 mhz is the typical input clock frequency and low power mode is selected. ms0=nclk or vcc to select hpr (high precision): f clk = 2 mhz is the typical input clock frequency and accuracy is enhanced. for the stpms2h, lpr mode is not used and the settings should be chosen between ms0=nclk or vcc. in this case, f clk = 4 mhz is typical. the relative gain of the current channel is selectable between 2 or 16, which defines the maximum differential voltage on the current channel to 300 mv or 37.5 mv, respectively. the voltage channel gain setting is fixed at 2, which defines the maximum differential voltage on the voltage channel inputs to 300 mv. ms1 defines the temperature compensation (tc) curve of the internal voltage reference of the stpms2l, as described in ta bl e 9 . this bootstrap function is not used with the stpms2h. the temperature-compensated reference voltage generator produces v ref = 1.23 v. this generator is implemented as a band gap generator, whose temperature compensation curve can be selected through the ms1 configuration pin. ms2 defines the outputs of the device: the stpms2 sends to the dat and datn pins the sigma-delta streams synchronous to the clk signal. the output mode can be configured according to ta b l e 1 0 as follows: the output current channel's sigma-delta stream on dat and the voltage channel's sigma-delta stream on datn output multiplexed signals, so when clk = 0, the current channel output sigma-delta value is set on the dat pin, and when clk = 1, the voltage channel output sigma-delta value is set on the dat pin. the datn pin tracks dat, so datn = ~dat. output current channel's sigma-delta stream on dat and the current channel's sigma- delta stream negated on datn table 8. precision mode and input amplifier gain selection ms0 mode description gnd 0 lpr, amplifier gain selection g3 = 16 clk 1 lpr, amplifier gain selection g0 = 2 nclk 2 hpr, amplifier gain selection g0 = 2 vcc 3 hpr, amplifier gain selection g3 = 16 table 9. tc of the band-gap reference ms1 mode description gnd 0 tc = 60 ppm/c clk 1 flattest tc = +30 ppm/c nclk 2 tc = +160 ppm/c vcc 3 tc = -160 ppm/c
stpms2 theory of operation doc id 16525 rev 3 23/33 ms3 enables or disables the bist dac output levels. if enabled (ms3=vcc), the input of the modulators are disconnected from pin vip, vin and cip, and cin, and connected to the output of bist dac which generates 2 different levels appropriately adjusted for the current channel 300 mv / 37.5 mv depending on gain settings 2/16, while for the voltage channel, 300 mv is used. this mode is used as auto diagnostic methodology of good behavior of the two modulators. when disabled (ms3=gnd), the input of the modulators comes from pins vip, vin and cip, and cin. this is the normal operating condition. 8.5 soft mode the stpms2 switches to soft mode when ms3 is connected to clk. in soft mode, input pins ms0, ms1 and ms2 control the serial communication port, as described in ta bl e 1 2 . this way, all settings of the 40 internal c onfiguration bits can be changed. the old values remain in the registers until they are overwritten. table 10. control of voltage channel and output signals ms2 mode description gnd 0 voltage channel on, datn = ~ [dat =(clk) ? bsv : bsc)] clk 1 voltage channel off, datn = bscn, dat = bsc nclk 2 voltage channel off, datn = bscn, dat = bsc vcc 3 voltage channel on, datn = bsc, dat = bsv table 11. selection of hard, soft or test mode and enable of bist ms3 mode description gnd 0 hardmode, bist mode off clk 1 soft mode nclk 2 reserved vcc 3 hardmode, bist mode on table 12. pins for spi communication pin function description ms0 scl clock input ms1 tdi data input ms2 tds enable ms3 clk spi operation
theory of operation stpms2 24/33 doc id 16525 rev 3 table 13. description of output signals and configuration bits cfg[39:0] hard mode soft mode internal signal description ms0 cfg[0] lp/hp operating mode: lp/hp=0: lpr lp/hp=1: hpr ms0 cfg[1] gain gain selector of current channel pre-amplifier: gain=0: x2 gain=1: x4 gain=2: x8 gain=3: x16 ms0 cfg[2] ms1 cfg[3] tc temperature compensation of voltage reference: tc=0: tc = 60 ppm/c tc=1: flattest tc = +30 ppm/c tc=2: tc = +160 ppm/c tc=3: tc = -160 ppm/c ms1 cfg[4] ms2 cfg[5] domul output multiplexer enable: domul=0: outputs not multiplexed domul=1: outputs multiplexed ms2 cfg[6] pdv power-down of voltage modulator: pdv=0: voltage modulator on pdv=1: voltage modulator off ms3 cfg[7] ebistc current modulator bist dac enable: ebistc=0: bistc disabled ebistc=1: bistc enabled ? ebistc frequency output 0 0 1 clk/2 15 x lfc ms3 cfg[8] ebistv voltage modulator bist dac enable: ebistc=0: bistv disabled ebistc=1: bistv enabled ? ebistv frequency output 0 0 1 clk/2 15 x lfv ms3 cfg[9] einchpc cip, cin input pin enable: einchpc=0: cin cip disabled einchpc=1: cin cip enabled ms3 cfg[10] einchpv vip, vin input pin enable: einchpc=0: vi n vip disabled einchpc=1: vin vip enabled 1 cfg[11] echplfc low frequency chopper of current modulator enable: echplfc=0: lfc disabled echplfc=1: lfc enabled (1)
stpms2 theory of operation doc id 16525 rev 3 25/33 hard mode soft mode internal signal description 1cfg[12] mc lfc of current channel frequency selector: ? mc[2:0] frequency 000 clk/1024 001 (1) clk/512 010 clk/256 011 clk/128 100 clk/64 101 (2) clk/64 110 (2) clk/64 111 (2) clk/64 0cfg[13] 0cfg[14] 1 cfg[15] echphfc high frequency chopper of current modulator enable: echphfc=0: hfc disabled echphfc=1: hfc enabled (1) 1cfg[16] nc hfc of current channel frequency selector ? nc[2:0] frequency 000 (2) clk/256 001 (2) clk/128 010 clk/256 011 (1) clk/128 100 clk/64 101 clk/32 110 clk/16 111 clk/8 1cfg[17] 0cfg[18] 1cfg[19]echplfv low frequency chopper of voltage modulator enable: echplfv=0: lfv disabled echplfv=1: lfv enabled (1) 1cfg[20] mv lfc of voltage channel frequency selector: ? mv[2:0] frequency 000 clk/1024 001 (1) clk/512 010 clk/256 011 clk/128 100 clk/64 101 (2) clk/64 110 (2) clk/64 111 (2) clk/64 0cfg[21] 0cfg[22] 1 cfg[23] echphfv high frequency chopper of voltage modulator enable: echphfc=0: hfv disabled echphfc=1: hfv enabled (1) table 13. description of output signals and configuration bits cfg[39:0] (continued)
theory of operation stpms2 26/33 doc id 16525 rev 3 hard mode soft mode inte rnal signal description 1cfg[24] nv hfc of voltage channel frequency selector: ? nv[2:0] frequency 000 (2) clk/256 001 (2) clk/128 010 clk/256 011 (1) clk/128 100 clk/64 101 clk/32 110 clk/16 111 clk/8 1cfg[25] 0cfg[26] 1 cfg[27] eprsc current modulator pseudo random signals enable: eprsc=0: prsc disabled eprsc=1: prsc enabled (1) 1 cfg[28] eprsv voltage modulator pseudo random signals enable: eprsv=0: prsv disabled eprsv=1: prsv enabled (1) 0 cfg[29] - reserved 0 cfg[30] - reserved 0 cfg[31] - reserved 0cfg[32] dtmc dat and dat output signal selector: ? dtmc[5:0] pdv domul dat datn 00xxxx 0 0 bsv bsc 00xxxx 0 1 (bsv,bsc) (bsvn,bscn) 00xxxx 1 0 bsc bscn 00xxxx 1 1 bsc bscn 01xx00 0 0 bsv lfc 01xx01 0 1 (bsv,bsc) hfc 01xx10 1 0 bsc bistc 01xx11 1 1 bsc prsc 1000xx 0 0 lfv bsc 1001xx 0 1 hfv (bsvn,bscn) 1010xx 1 0 bistv bscn 1011xx 1 1 prsv bscn 110000 x x lfv lfc 110101 x x hfv hfc 111010 x x bistv bistc 111111 x x prsv prsc 0cfg[33] 0cfg[34] 0cfg[35] 0cfg[36] 0cfg[37] 0 cfg[38] - reserved 0 cfg[39] - reserved 1. default value for hard mode 2. combinations not used table 13. description of output signals and configuration bits cfg[39:0] (continued)
stpms2 theory of operation doc id 16525 rev 3 27/33 8.5.1 writing to the configur ation register in soft mode all 40 configuration bits must be overwritten. 1. after power-on reset, soft mode is selected (ms3=clk), the bits ms0 .. ms2 must be stable at least 5*clk 2. after switching into soft mode (ms3=clk), the bits ms0 .. ms2 must be stable at least 2*clk. the same rule applies when switching from soft mode to hard mode: ms0 .. ms2 must be stable at least 2*clk figure 20. timings to switch to soft mode after por am09 8 97v1 new values clk ms1/tdi ms0/scl ms2/tds cfg[0] cfg[1] cfg[2] cfg[38] cfg[39] ms3/clk cfg delay 1 figure 21. timings to switch to soft mode am09 8 9 8 v1 new values clk ms1/tdi ms0/scl ms2/tds cfg[1] cfg[2] cfg[3] cfg[38] cfg[39] ms3/clk cfg delay 2 cfg[0] old values hard mode
package mechanical data stpms2 28/33 doc id 16525 rev 3 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 14. qfn16 (4 x 4 mm.) mechanical data dim. mm. min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a3 0.20 b 0.25 0.30 0.35 d 3.90 4.00 4.10 d2 2.50 2.80 e 3.90 4.00 4.10 e2 2.50 2.80 e0.65 l 0.30 0.40 0.50
stpms2 package mechanical data doc id 16525 rev 3 29/33 figure 22. qfn16 (4 x 4 mm.) drawing 7571203_a
package mechanical data stpms2 30/33 doc id 16525 rev 3 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n 99 101 3 . 898 3 . 9 76 t 14.4 0.567 ao 4. 3 5 0.171 bo 4. 3 5 0.171 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx (4x4) mechanical data
stpms2 package mechanical data doc id 16525 rev 3 31/33 figure 23. qfn16 (4 x 4) footprint recommended data (dimension in mm.)
revision history stpms2 32/33 doc id 16525 rev 3 10 revision history table 15. document revision history date revision changes 23-oct-2009 1 initial release. 06-jul-2011 2 document status promot ed from preliminary data to datasheet. 11-oct-2011 3 modified: 100 f ==> 100 nf section 8.2 on page 17 .
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